A flash memory is a non-volatile electrically erasable data storage device that evolved from electrically erasable programmable read-only memory (EEPROM). The two main types of flash memory are named after the logic gates that their storage cells resemble: NAND and NOR. NAND flash memory is commonly used in solid-state drives, which are supplanting magnetic disk drives in many applications. A NAND flash memory is commonly organized as multiple blocks, with each block organized as multiple pages. Each page comprises multiple cells. Each cell is capable of storing an electric charge. Some cells are used for storing data bits, while other cells are used for storing error-correcting code (ECC) bits. A cell configured to store a single bit is known as a single-level cell (SLC). A cell configured to store two bits is known as a multi-level cell (MLC). In an MLC cell, one bit is commonly referred to as the least-significant bit (LSB), and the other as the most-significant bit (MSB). A cell configured to store three bits is known as a triple-level cell (TLC). Writing data to a flash memory is commonly referred to as “programming” the flash memory, due to the similarity to programming an EEPROM.
The electric charge stored in a cell can be detected in the form of a cell voltage. To read an SLC flash memory cell, the flash memory controller provides one or more reference voltages (also referred to as read voltages) to the flash memory device. Detection circuitry in the flash memory device will interpret the bit as a “0” if the cell voltage is greater than a reference voltage Vref and will interpret the bit as a “1” if the cell voltage is less than the reference voltage Vref. Thus, an SLC flash memory requires a single reference voltage Vref. In contrast, an MLC flash memory requires three such reference voltages, and a TLC flash memory requires seven such reference voltages. Thus, reading data from an MLC or TLC flash memory device requires that the controller provide multiple reference voltages having optimal values that allow the memory device to correctly detect the stored data values.
Determining or detecting stored data values using controller-provided reference voltages is hampered by undesirable physical non-uniformity across cells of a device that are inevitably introduced by the fabrication process, as such non-uniformity results in the reference voltages of different cells that store the same bit value being significantly different from each other. The detection is further hampered by reference voltages changing over time due to adverse effects of changes in temperature, interference from programming neighboring cells, and numerous erase-program cycles. Errors in detecting stored data values are reflected in the performance measurement known as bit error rate (BER). The use of ECC can improve BER to some extent, but the effectiveness of ECC diminishes as improved fabrication processes result in smaller cell features.
Conventional methods for aiding the detection of stored data values using reference voltages commonly rely upon an assumption that the reference voltage windows for a device have Gaussian distributions. As illustrated in FIG. 1, an MLC flash memory has four cell voltage distributions 102, 104, 106 and 108 with four respective mean target cell voltages Vtarget0 112, Vtarget1 114, Vtarget2 116 and Vtarget3 118. Such cell voltage distributions commonly overlap each other slightly, but such overlap is not shown in FIG. 1 for purposes of clarity. During a read operation, to attempt to characterize or detect the two bits of cell data (i.e., the LSB and MSB) a flash memory device (not shown) uses three reference voltages it receives from a flash memory controller (not shown): Vref0 122, Vref1 124 and Vref2 126. More specifically, the flash memory device compares the cell voltage with Vref1 124 to attempt to detect the LSB. If the flash memory device determines that the cell voltage is less than Vref1 124, i.e., within a window 128, then the flash memory device characterizes the LSB as a “1”. If the flash memory device determines that the cell voltage is greater than Vref1 124, i.e., within a window 130, then the flash memory device characterizes the LSB as a “0”. The flash memory device also compares the cell voltage with Vref0 122 and Vref2 126 to attempt to detect the MSB. If the flash memory device determines that the cell voltage is between Vref0 122 and Vref2 126, i.e., within a window 132, then the flash memory device characterizes the MSB as a “0”. If the flash memory device determines that the cell voltage is either less than Vref0 122 or greater than Vref2 126, i.e., within a window 134, then the flash memory device characterizes the MSB as a “1”.
Despite the benefits of conventional methods for aiding the detection of stored data values, such as the use of ECC, a page read sometimes fails. That is, the BER is so great that ECC decoding is unable to correct all erroneous bits. A common method for responding to such a page read failure is known as a “retry” or “read retry.” Although various read retry methods are known, a common characteristic among them is that they adjust the candidate reference voltage by incrementing or decrementing it by a fixed amount (ΔV) and then try to read the page a second time using the adjusted candidate reference voltage. If there is a second page read failure, the methods again adjust the candidate reference voltage by incrementing or decrementing it and try to read the page a third time using the adjusted reference voltage. The manner in which the methods adjust the candidate reference voltage generally follows a straightforward pattern. For example, on the first retry after a page read failure a method can increment the original reference voltage Vref to a value Vref+ΔV. If there is a second page read failure, then on the second retry the method can decrement the original reference voltage Vref to a value Vref−ΔV. If there is a third page read failure, then on the third retry the method can increment the original reference voltage Vref to a value Vref+2ΔV. If there is a fourth page read failure, then on the fourth retry the method can decrement the original reference voltage Vref to a value Vref−2ΔV. Such a pattern can continue in this manner, with the method adjusting the candidate reference voltage to successively more positive values alternating with successively more negative values. In other words, the method searches for a reference voltage that results in a successful page read by broadening the search outwardly from a midpoint defined by the reference voltage used on the initial page read that failed.
Such conventional read retry methods that blindly search for a reference voltage that results in a successful page read can be slow and therefore adversely impact memory throughput. Such methods can severely impact memory throughput in a system having TLC flash memory because the upper page read uses four reference voltages, causing an exponential increase in read retry time. It would be desirable to enable a flash memory controller to determine an optimal reference voltage by performing a minimal number of read retries.